Data receiver of semiconductor integrated circuit

ABSTRACT

A data receiver of a semiconductor integrated circuit is configured to detect received data using an equalization function, wherein the data receiver is configured to stop the equalization function during a period in which the data is not received.

This application is a continuation application of application Ser. No.12/176,215, titled “Data Receiver of Semiconductor Integrated Circuitand Method for Controlling the Same,” filed Jul. 18, 2008, which ishereby incorporated by reference.

BACKGROUND

1. Technical Field

The embodiments described herein relate to a semiconductor integratedcircuit, particularly a data receiver of a semiconductor integratedcircuit.

2. Related Art

A conventional data receiver of a semiconductor integrated circuit, asshown in FIG. 1, includes termination resistors R1_T, R2_T connectedbetween a terminal of a power voltage VDD and a terminal of a groundvoltage VSS, an amplifier 10, a delay chain 20, and a latch 30.

The amplifier 10 can amplify received data on the basis of a referencevoltage VREF received from the outside and output the amplified signal“AMP_OUT”. The amplifier 10 can include a circuit for an equalizationfunction. An equalization function is a technology for improving theoperational margin of the data receiver that operates at a high speed byusing past date to detect present data.

The amplifier 10 uses feedback data EQ− and EQ+ as past data. One of thefeedback data, EQ− or EQ+, has the same logic value as the amplifiedsignal “AMP_OUT” and the other feedback data has an opposite logicvalue. The delay chain 20 can delay and transmit the amplified signal“AMP_OUT” to the latch 30. The latch 30 can latch the amplified signal“AMP_OUT” based on the clock signal “CLK”.

A conventional data receiver of a semiconductor integrated circuit canuse the equalization function. The amplified signal “AMP_OUT”, outputfrom the amplifier 10, can be maintained at high impedance state High-Zby the termination resistors R1_T, R2_T in a period in which data isreceived. The high impedance state can have a level of (VDD−VSS)/2, i.e.an inaccurate logic level that may be recognized as a high level or alow level.

The high-impedance amplified signal “AMP_OUT”, having an inaccuratelogic level in the period when data is not received, can be fed-backusing the feedback data to the amplifier 10 through the delay chain 20.Accordingly, since the feedback data can have an inaccurate logic levelin the period when data is not received, the amplifier 10 may notaccurately detect data received after a high impedance level.

SUMMARY

An embodiment, a data receiver of a semiconductor integrated circuitbeing configured to detect received data using an equalization function,wherein the data receiver is configured to stop the equalizationfunction during a period in which the data is not received.

These and other features, aspects, and embodiments are described belowin the section entitled “Detailed Description.”

BRIEF DESCRIPTION OF THE DRAWINGS

Features, aspects, and embodiments are described in conjunction with theattached drawings, in which:

FIG. 1 a diagram illustrating the configuration of a conventional datareceiver of a semiconductor integrated circuit.

FIG. 2 is a diagram illustrating the configuration of a data receiver ofa semiconductor integrated circuit according to one embodiment.

FIG. 3 is a diagram illustrating the configuration of a detecting unitthat can be included in the receiver illustrated FIG. 2.

FIG. 4 is a diagram illustrating the configuration of an equalizationfunction control unit that can be included in the receiver illustratedFIG. 2.

FIG. 5 is a view showing output waveforms of units in a data receiver ofa semiconductor integrated circuit according to one embodiment.

DETAILED DESCRIPTION

The embodiments described herein relate to a data receiver of asemiconductor integrated circuit. FIG. 2 is a diagram illustrating theconfiguration of a data receiver 101 of a semiconductor integratedcircuit according to one embodiment. Referring to FIG. 2, the datareceiver 101 can include resistors R1_T, R2_T, an amplifier 100, a delaychain 200, a latch 300, a detecting unit 400, a capacitor C1, and anequalization function control unit 500.

The configuration of the termination resistors R1_T, R2_T, the amplifier100, the delay chain 200, and the latch 300 can be a conventionalconfiguration that is well known and thus is not described in detailherein. However, the amplifier 100 can perform the equalization functionwhen feedback data (EQ− and EQ+) have opposite logic levels, and canstop the equalization function when the feedback data EQ−, EQ+ has thesame logic levels, for example, a low level. Further, depending on theconditions of the circuit design, the amplifier 100 may be designed tostop the equalization function when the feedback data EQ−, EQ+ has ahigh level.

The detecting unit 400 can output a section detecting signal “HZDET”when detecting a period in which data is not received by the amplifier100, according to the level of the amplified signal “AMP_OUT”. The levelof an input terminal of the amplifier 100 can be maintained at a highimpedance state during the period in which data is not received by theamplifier 100. Therefore, the detecting unit 400 can output the sectiondetecting signal “HZDET” when detecting a period when data is notreceived, by using the amplified signal “AMP_OUT”, sent from theamplifier 100, according to a high impedance state. The capacitor C1 canoperate as a filter for removing a glitch that may be included in thesection detecting signal “HZDET”, e.g. noise, through the operation ofthe detecting unit 400.

FIG. 3 is a diagram illustrating the configuration of the detecting unit400, which can be included in the receiver, illustrated FIG. 2.Referring to FIG. 3, the detecting unit 400, can include first andsecond transistors MN1, MP1, first and second resistors R11, R12, aninverter IV1, and an AND gate AND1.

The first transistor MN1 can output a first data level detecting signal“HDET” at a low level, when the level of an amplified signal “AMP_OUT”is above a first voltage level, i.e. above the voltage level of(VDD_VSS)/2 at a high impedance state. The amplified signal “AMP_OUT”can be received at a gate of first transistor MN1, a ground voltage VSScan be applied to a source, and a power voltage VDD can be applied to adrain through the first resistor R11.

The second transistor MP1 can output a second data level detectingsignal “LDET” at a high level when the level of an amplified signal“AMP_OUT” is less than the voltage level of (VDD−VSS)/2 at the highimpedance state. The amplified signal “AMP_OUT” can be received at agate of the second transistor MP1, a power voltage VDD can be applied toa source, and a ground voltage VSS can be applied to a drain through thesecond resistor R22.

The first and second transistors MN1 and MP1 can be designed to have alow threshold voltage. The first and second resistors R11 and R12 can bedesigned to have a high resistance value such that both of the first andsecond transistors, MN1 and MP1, can be turned on and low-level andhigh-level voltages are separately generated, at a voltage level of(VDD−VSS)/2 determined by a high impedance state. The inverter IV1 canreceive the first data level detecting signal “HDET”. The AND gate AND1can output the section detecting signal “HZDET” by performing an ORoperation on an output of the inverter IV1 and the second data leveldetecting signal “LDET”.

FIG. 4 is a diagram illustrating the configuration of the equalizationfunction control unit 500, which can be included in the diagram,illustrated FIG. 2. Referring to FIG. 4, the equalization functioncontrol unit 500 can stop the equalization function of the amplifier 100by changing the feedback data (EQ− and EQ+) to the level of the groundpower in response to the section detecting signal “HZDET”. Theequalization function control unit 500 can include third and fourthtransistors MN2 and MN3. The third transistor MN2 can connect a signalline, which can transmit the feedback data, e.g. EQ+, in response to thesection detecting signal “HZDET”, to a terminal of the ground voltageVSS. The fourth transistor MN3 can connect a signal line, which cantransmit the feedback data, e.g. EQ−, in response to the sectiondetecting signal “HZDET”, to the terminal of the ground voltage VSS.

FIG. 5 is a view showing output waveforms of units in a data receiver ofa semiconductor integrated circuit according to one embodiment describedherein. As shown in FIG. 5, the input IN of the amplifier 100 can be atthe high impedance state High-Z in the period in which data is notreceived. Since the input IN can be at the high impedance state High-Z,the level of the amplified signal “AMP_OUT” sent from the amplifier 100can be equal to (VDD−VSS)/2.

When the level of the amplified signal “AMP_OUT” is (VDD−VSS)/2, thefirst transistor MN1 of the detecting unit 400 shown in FIG. 3 canoutput a first data level detecting signal “HDET” at a low level and thesecond transistor MP1 can output a second data level detecting signal“LDET” at a high level. Since the first data level detecting signal“HDET” can be at a low level and the second data level detecting signal“LDET” can be at a high level, a section detecting signal “HZDET” can beoutput at a high level.

Furthermore, since the section detecting signal “HZDET” can be at a highlevel, both the third and fourth transistors, MN2 and MN3, of theequalization function control unit 500, shown in FIG. 4, can be turnedon and change the feedback data (EQ− and EQ+) to a low level, whileconnecting the signal lines, which can transmit the feedback data to theterminals of the ground voltage VSS. Furthermore, as both of thefeedback data is changed to a low level, the equalization function ofthe amplifier 100 can be stopped. That is, the equalization function ofthe amplifier 100 can be stopped when data is not received (EQDisabled).

Meanwhile, once data at a specific level, e.g. high-level data, startsto be received and an amplified, signal “AMP_OUT” can be changed to ahigh level. Since the amplified signal “AMP_OUT” can be at a high level,i.e. at the same level as the power voltage VDD, the first transistorMN1 of the detecting unit 400, shown in FIG. 3, can output a first datalevel detecting signal “HDET” at a high level, and the second transistorMP1 can output a second data level detecting signal “LDET” at a highlevel. Since the first data level detecting signal “HDET” can be at ahigh level and the second data level detecting signal “LDET” can be at ahigh level, a section detecting signal “HZDET” can be output at a lowlevel.

Furthermore, since the section detecting signal “HZDET” can be at a lowlevel, the third and fourth transistors, MN2 and MN3, of theequalization function control unit 500, shown in FIG. 4, can both beturned off. In addition, since the feedback data, EQ− and EQ+, can haveopposite logic levels, i.e. normal levels, the equalization of theamplifier 100 can be performed. That is, the equalization function ofthe amplifier 100 can be performed in a period when data is normallyreceived (EQ Enabled). On the other hand, even if data at a low levelstarts to be received and an amplified signal “AMP_OUT” is changed to alow level, the equalization function of the amplifier 100 can beperformed normally via the same operation as when data at a high levelis received.

While certain embodiments have been described above, it will beunderstood that the embodiments described are by way of example only.Accordingly, the apparatus described herein should not be limited basedon the described embodiments. Rather, the apparatus described hereinshould only be limited in light of the claims that follow when taken inconjunction with the above description and accompanying drawings.

1. A data receiver of a semiconductor integrated circuit, beingconfigured to detect received data using an equalization function,wherein the data receiver is configured to stop the equalizationfunction during a period in which the data is not received.
 2. The datareceiver of claim 1 comprising: an amplifier configured to output anamplified signal by detecting and amplifying the data using theequalization function according to feedback data; a detecting unitconfigured to detect the period in which data is not received in theamplifier and output a detecting signal; and an equalization functioncontrol unit configured to stop the equalization function of theamplifier in response to the detecting signal.
 3. The data receiver ofclaim 2, wherein the detecting unit is configured to detect the periodin which data is not received by the amplifier according to the level ofthe amplified signal.
 4. The data receiver of claim 3, wherein thedetecting unit comprises: a first switching element configured to outputa signal at a first logic level when the level of the amplified signalis above a first voltage level; a second switching element configured tooutput a signal at a second logic level when the level of the amplifiedsignal is less than the first voltage level; and a logic circuitconfigured to output the detecting signal by combining the output of thefirst switching element and the output of the second switching element.5. The data receiver of claim 4, wherein the first voltage levelincludes a middle level between a power voltage level and a groundvoltage level.
 6. The data receiver of claim 5, wherein the firstswitching element is a transistor with a gate configured to receive theamplified signal, a source configured to be applied with the groundvoltage, and a drain configured to be applied with the power voltagethrough a first resistor.
 7. The data receiver of claim 5, wherein thesecond switching element is a transistor with a gate configured toreceive the amplified signal, a source configured to be applied with thepower voltage, and a drain configured to be applied with the groundvoltage through a second resistor.
 8. The data receiver of claim 4,wherein the logic circuit is configured to output the detecting signalby performing an AND operation on an inverted signal obtained byinverting the signal of first logic level, and the signal of secondlogic level.
 9. The data receiver of claim 2, wherein the equalizationfunction control unit is configured to stop an equalization function ofthe amplifier by controlling the level of the feedback data in responseto the detecting signal.
 10. The data receiver of claim 9, wherein theequalization function control unit is configured to change a voltagelevel of the feedback data to the ground voltage level in response tothe detecting signal.
 11. The data receiver of claim 10, wherein theequalization function control unit includes switching elements thatconnect signal lines to terminals of the ground voltage, wherein thesignal lines are configured to transmit the feedback data in response tothe detecting signal.